View BU1852GUW12_5474515.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

bu1852guw 1/25 www.rohm.com 2012.08 - rev.b ? 2012 rohm co., ltd. all rights reserved. gpio ics keyencoder ic bu1852guw, bu1852gxw description keyencoder ic bu1852 can monitor up to 8x12 matrix (96 keys), which means to be adaptable to qwerty keyboard. we adopt the architecture t hat the information of the only key wh ich status is changed, like push or release, is encoded into the 8 bits data. this can greatly reduce the cpu load which t ends to become heavier as the number of keys increase. (previously, all key's status is stored in the registers.) when the num ber of keys is small, t he extra ports can be used as gpio. furthermore, auto sleep function contributes to low po wer consumption, when no keys are pressed. it is also equipped with the various functions such as ghost key reject ion, n-key rollover, built-in power on reset and oscillator. features 1) monitor up to 96 matrix keys. 2) under 3a stand-by current 3) built-in power on reset. 4) ghost key rejection. 5) keyscan / gpio selectable 6) 3 volt tolerant input absolute maximum ratings (ta=25 ) parameter symbol ratings unit conditions supply voltage vdd -0.3 ~ +2.5 v vdd Q vddio vddio -0.3 ~ +4.5 v input voltage vi1 -0.3 ~ vdd +0.3 1 v xrst, xi, tw, porenb vi2 -0.3 ~ vddio +0.3 1 v adr vit -0.3 ~ +4.5 v xint, scl, sda, col[11:0], row[7:0] storage temperature range tstg -55 ~ +125 package power pd 272 2 mw this ic is not designed to be x-ray proof. 1 it is prohibited to exceed the absolute maximum ratings even including +0.3 v. 2 package dissipation will be reduced each 2.72mw/ when the ambient temperature increases beyond 25 . operating conditions parameter symbol ratings unit conditions min. typ. max. supply voltage range (vdd) vdd 1.65 1.80 1.95 v supply voltage range (vddio) vddio 1.65 1.80 3.60 v input voltage range vi1 -0.2 - vdd+0.2 v xrst, xi, tw, porenb vi2 -0.2 - vddio+0.2 v adr vit -0.2 - 3.60 v xint, scl, sda, col[11:0], row[7:0] operating temperature range topr -30 25 +85 no.11098ebt04
technical note 2/25 bu1852guw, bu1852gxw www.rohm.com 2012.08 - rev.b ? 2012 rohm co., ltd. all rights reserved. electrical characteristics 1. dc characteristics (vdd=1.8v, vddio=1.8v, ta=25 ) parameter symbol limits unit conditions min. typ. max. input h voltage1 v ih1 0.8xvdd - 3.6 v 1 input h voltage2 v ih2 0.8xvdd - vdd+0.2 v 2 input h voltage3 v ih3 0.8xvddio - 3.6 v col[11:0] input h voltage4 v ih4 0.8xvddio - vddio+0.2 v adr input l voltage1 v il1 -0.2 - 0.2xvdd v 3 input l voltage2 v il2 -0.2 - 0.2xvddio v adr, col[11:0] input h current1 i ih1 -1.0 - 1.0 a v in =3.60v 4 pull-down/up off input h current2 i ih2 -1.0 - 1.0 a v in =1.80v 5 input l current i il -1.0 - 1.0 a v in =0v pull-down/up off output h voltage1 v oh1 0.75xvdd - - v i oh =-2ma, row[7:0] output h voltage2 v oh2 0.75xvddio - - v i oh =-2ma, col[11:0] output l voltage1 v ol1 - - 0.25xvdd v i ol =2ma, 6 output l voltage2 v ol2 - - 0.25xvddio v i ol =2ma, col[11:0] 1 xint,scl,sda,row[7:0] 2 xrst,xi,tw,porenb 3 xint,scl,sda,row[7:0],xrst,xi,tw,porenb 4 xint,scl,sda,row[7:0],col[11:0] 5 xrst,xi,tw,porenb,adr 6 xint,sda,row[7:0] 2. circuit current (vdd=1.8v, vddio=1.8v, ta=25 ) parameter symbol limits unit conditions min. typ. max. power down current (vdd) i pd - - 1.0 a xrst=vss power down current (vddio) i pdio - - 1.0 a standby current1 (vdd) i stby1 - - 3.0 a xrst=vdd, porenb=vss, scl=vdd, sda=vdd standby current1 (vddio) i stbyio1 - - 1.0 a standby current2 (vdd) i stby2 - - 1.0 a xrst=vdd, porenb=vdd, scl=vdd, sda=vdd standby current2 (vddio) i stbyio2 - - 1.0 a operating current (vdd) i op - 50 110 a internal oscillator is used. one key is pressed.
technical note 3/25 bu1852guw, bu1852gxw www.rohm.com 2012.08 - rev.b ? 2012 rohm co., ltd. all rights reserved. 3. i 2 c ac characteristics fig.1 i 2 c ac timing vdd=1.8v, vddio=1.8v, topr=25 , tw=vss parameter symbol limits unit conditions min. typ. max. scl clock frequency f scl - - 400 khz bus free time t buf 1.3 - - s (repeated) start condition setup time t su;sta 0.6 - - s (repeated) start condition hold time t hd;sta 0.6 - - s scl low time t low 1.3 - - s scl high time t high 0.6 - - s data setup time t su;dat 100 - - ns data hold time t hd;dat 0 - - ns stop condition setup time t su;sto 0.6 - - s scl sda t su;sta (repeated) start bit7 ack stop condition bit6 t low t high t hd;sta t su;dat t hd;dat t su;sto t buf 1/f sclk
technical note 4/25 bu1852guw, bu1852gxw www.rohm.com 2012.08 - rev.b ? 2012 rohm co., ltd. all rights reserved. 4. gpio ac characteristics fig.2 gpio ac timing vdd=1.8v, vddio=1.8v, topr=25 , tw=vss parameter symbol limits unit conditions min. typ. max. output data valid time t dv - - 0.8 s interrupt valid time t iv - - 5 s interrupt reset time t ir - - 5 s scl gpio[7:0](output) t dv a na state bit 0 bit 1 xint t iv gpio[7:0](input) t ir
technical note 5/25 bu1852guw, bu1852gxw www.rohm.com 2012.08 - rev.b ? 2012 rohm co., ltd. all rights reserved. 5. startup sequence fig.3 start sequence timing vdd=1.8v, vddio=1.8v, topr=25 , tw=vss parameter symbol limits unit conditions min. typ. max. vdd stable time t vdd - - 5 ms vdd and vddio are on at the same time. reset wait time t rwait 0 - - s xrst controlling 1 reset valid time t rv 10 - - s i 2 c wait time t i2cwait 10 - - s 1 even if xrst port is not used, it operates because power on reset is built in. in this case, connect xrst port with vdd on the set pcb. note) at vdd=0v, when scl port is changed from 0v to 0.5v or more, scl port pulls the current. it is same in sda, xint, and row[7:0] ports of 3v tolerant i/o. (v ddio=0v in case of col[11:0] ports) fig.4 port operating at vdd=0v vdd vddio xrst scl sda t vdd t vdd t rwait t i2cwait t rv t i2cwait t vdd t rwait t vdd vdd port (~2k pull-up) 0v 3v port pull current 2 3ms 0.1 1ma 0v
technical note 6/25 bu1852guw, bu1852gxw www.rohm.com 2012.08 - rev.b ? 2012 rohm co., ltd. all rights reserved. u1852 lot no. package specification fig.5 package specif ication (vbga035w040)
technical note 7/25 bu1852guw, bu1852gxw www.rohm.com 2012.08 - rev.b ? 2012 rohm co., ltd. all rights reserved. fig.6 package specification (ubga035w030) lot no.
technical note 8/25 bu1852guw, bu1852gxw www.rohm.com 2012.08 - rev.b ? 2012 rohm co., ltd. all rights reserved. pin assignment fig.7 pin diagram (top view) block diagram fig.8 functional block diagram testm0 xi row0 row2 row4 xrs t row1 row3 row6 xint vdd porenb vss row 7 sd a vdd vddio vss col2 scl col10 col8 col6 col4 1 2 3 4 5 a b c d e tw row5 col0 col1 col3 6 testm1 col11 col9 col7 col5 f a dr key scan / gpio control i 2 c / 3 wire control xint scl sda xrst col[11:0]/ gpio[19:8] vdd power on reset vss reset gen row[7:0]/ gpio[7:0] oscillator key encoder + fifo testm[1:0] xi porenb adr tw interrupt filter interrupt logic input filter vddio
technical note 9/25 bu1852guw, bu1852gxw www.rohm.com 2012.08 - rev.b ? 2012 rohm co., ltd. all rights reserved. pin functional descriptions pin name i/o function init cell type vdd - power supply (core, i/o except for col[11:0], adr) - - vddio - power supply (i/o for col[11:0], adr) - - vss - gnd - - xrst i reset(low active) i a xi i external clock input (32khz) i i tw i select protocol h: original 3 wire l: i 2 c i b adr i (tw=l) select device address for i 2 c (tw=h) h : key scan rate 1/2 l : key scan rate original i b xint o key/gpio interrupt h(tw=h) hi-z(tw=l) e scl i clock for seri al interface i d sda i/o serial data inout for serial interface i f row0 i/o row0 / gpio0 i [100k ? pull-up] g row1 i/o row1 / gpio1 row2 i/o row2 / gpio2 row3 i/o row3 / gpio3 row4 i/o row4 / gpio4 row5 i/o row5 / gpio5 row6 i/o row6 / gpio6 row7 i/o row7 / gpio7 col0 i/o col0 / gpio8 l(tw=h) i [150k ? pull-down] (tw=l) h col1 i/o col1 / gpio9 col2 i/o col2 / gpio10 col3 i/o col3 / gpio11 col4 i/o col4 / gpio12 col5 i/o col5 / gpio13 col6 i/o col6 / gpio14 col7 i/o col7 / gpio15 col8 i/o col8 / gpio16 col9 i/o col9 / gpio17 col10 i/o col10 / gpio18 col11 i/o col11 / gpio19 porenb i power on reset enable (low active) i b testm0 i te s t p i n s 1 i c testm1 i 1 note: all these pins must be tied down to gnd in normal operation.
technical note 10/25 bu1852guw, bu1852gxw www.rohm.com 2012.08 - rev.b ? 2012 rohm co., ltd. all rights reserved. i/o equivalence circuit a b c d e f g h i fig.9 equivalent i/o circuit diagram
technical note 11/25 bu1852guw, bu1852gxw www.rohm.com 2012.08 - rev.b ? 2012 rohm co., ltd. all rights reserved. functional description 1. power mode the device enters the state of power down when xrst=? 0?. when xrst becomes high after powered, the device enters the standby state. power on reset a power on reset logic is implemented in this device. theref ore, it will operate correctly even if the xrst port is not used. in this case, the xrst port must be connected to ?1? (vdd), and the porenb port must be connected to ?0? (vss). if you don?t want to use power on reset, you must connect porenb port to ?1? (vdd). power down state the device enters power down state by xrst=?0?. an inte rnal circuit is initialized, and key encoding and 3wire/i 2 c interface are invalid. power on reset becomes inactive during this state. stand-by state the device enters the stand-by state by setting xrst to "1". in this state, the device is waiting for keys pressed or i 2 c communication (tw=?0?). when a key is pressed or i 2 c start condition, the state will change to operation. power on reset is active in this state if porenb = ?0?. operating state the device enters the operating state by pressing keys. the device will scan the key matrix and encode the key code, and then the 3wire/i 2 c interface tries to start communication by drivin g xint ?0?. see next section for the details. after communicating with host device, when no keys are pre ssed, the device returns to the stand-by state. power on reset is active in this state if porenb=?0?. 2. protocol of serial interface i 2 c when set to tw=?0?, scl and sda are used for i 2 c communication. any register shown in section 4 can be accessed through i 2 c. initially, all gpio ports are set to gpi and pull-up/down on. when the application requires gpo or key scan, proper register setting should be done through i 2 c. 3 wire (original) when set to tw=?1?, scl and sda are used for original 3w ire communication, which is not the standard interface. any register shown in section 4 cannot be accessed through 3wire. with tw=?1?, only keyscan and key encoding are supposed to be performed. gpio function is inactive . when the application needs kind of complex system (for instance, gpo+keyscan or gpio+keyscan?), i2c mode is recommended. see appendix for the details.
technical note 12/25 bu1852guw, bu1852gxw www.rohm.com 2012.08 - rev.b ? 2012 rohm co., ltd. all rights reserved. 3. i 2 c bus interface (tw=?0?) each function of gpio is contro lled by internal registers. the i 2 c slave interface is used to write or read those internal registers. the device supports 400khz fast-mode data transfer rate. slave address two device addresses (slave address) can be selected by adr port. a7 a6 a5 a4 a3 a2 a1 r/w adr=0 0 0 0 1 0 1 0 1/0 adr=1 0 0 0 1 1 0 1 data transfer one bit of data is transferred during scl = ?1?. during th e bit transfer scl = ?1? cycle, the signal sda should keep the value. if sda changes during scl = ?1?, start conditi on or stop condition occur and it is interpreted as a control signal. fig.10 data transfer start ? stop ? repeated start conditions when sda and scl are ?1?, the data isn?t transferred on the i 2 c bus. if scl remains ?1? and sda transfers from ?1? to ?0?, it means ?start condition? is occurred and access is started. if scl remains ?1? and sda transfers from ?0? to ?1?, it means ?stop condition? is occurred and access is stopped. it becomes repeat ed start condition (sr) the start condition enters again although the stop condition is not done. fig.11 start ? stop ? repeated start conditions sda scl data is valid when sda is stable sda is variable sda scl s s r start condition repeated start condition p stop condition
technical note 13/25 bu1852guw, bu1852gxw www.rohm.com 2012.08 - rev.b ? 2012 rohm co., ltd. all rights reserved. acknowledge after start condition is occurred, 8 bits data will be transferr ed. sda is latched by the rising edge of scl. after 8 bits data transfer is finished by the ?master?, ?master? opens sd a to ?1?. and then, ?slave? de-asserts sda to ?0? as ?acknowledge?. fig.12 acknowledge writing protocol register address is transferred after one byte of slave address with r/w bit. the 3 rd byte data is written to internal register which defined by the 2 nd byte. however, when the register address increased to the final address (18h), it will be reset to (00h) after the byte transfer. fig.13 writing protocol s a a a p data register address slave address transmit from maste r transmit from slave a = acknowledge a = not acknowledge s= start condition p= stop condition r / w=0(write) data a register address increment register address incremen t d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 x x x a 4 a 3 a 2 a 1 a 0 x x x x x x 0 x scl 1 2 8 9 sda output from master sda output from slave acknowledge not acknowledge s start condition clock pulse for acknowledgs
technical note 14/25 bu1852guw, bu1852gxw www.rohm.com 2012.08 - rev.b ? 2012 rohm co., ltd. all rights reserved. reading protocol after writing the slave address and read command bit, t he next byte is supposed to be read data. the reading register address is the next of the previous accessed address. reading address is incremented one by one. when the incremented address reaches t he last address, the following read address will be reset to (00h). 1 s a p transmit from master transmit from slave a=acknowledge a =not acknowledge s=start condition p=stop condition r/w=1(read) data a data a salve address xx x x x x x d7d6d5d4d3d2d1d0 d7d6d5d4d3d2d1d0 register address increment register address increment fig.14 readout protocol complex reading protocol there is the complex reading protocol to read the spec ific address of registers that master wants to read. after the specifying the internal register address as wr iting command, master occurs repeated start condition with read command. then, the reading access of the specified registers is supp osed to start. the register address increment is the same as normal reading protocol. if the addr ess is increased to the last, it will be reset to (00h). s a a a p transmit from master transmit from slave a=acknowledge a =not aclnowledge s=start condition p=stop condition sr=repeated start condition r/w=0(write) sr 1 r/w=1(read) a slave address xx xx xx 0 x register address x x x a4 a3 a2 a1 a0 slave address xx xx xxx data data register address increment d7 d6 d5 d4 d3 d2 d1 d0 register address increment d7 d6 d5 d4 d3 d2 d1 d0 a fig.15 complex reading protocol illegal access of i 2 c when illegal access happens, the data is annulled. the illegal accesses are as follows. ? the start condition or the stop condition is continuously generated. ? when the slave address and the r/w bit are written, repeated start condition or the stop condition are generated. ? repeated start condition or the stop condition is generated while writing data.
technical note 15/25 bu1852guw, bu1852gxw www.rohm.com 2012.08 - rev.b ? 2012 rohm co., ltd. all rights reserved. 4. register configuration table1 shows the register map and table2 indicates each functi on in the corresponding bit. only when tw is ?0?, these registers can be accessed with i 2 c. by making xrst ?0?, the setting register value will be initialized shown in following register map. table1 register map address init type d7 d6 d5 d4 d3 d2 d1 d0 00h 00h r/w reset reserved reserved reserved reserved reserved reserved reserved 01h 00h r/w reserved reserved reserved reserved reserved reserved reserved clksel 02h 11h r/w reserved ks_rate * 1 03h 00h r/w reserved reserved reserved reserved ks_c11 ks_c10 ks_c9 ks_c8 04h 00h r/w ks_c7 ks_c6 ks_c5 ks_c4 ks_c3 ks_c2 ks_c1 ks_c0 05h 00h r/w ks_r7 ks_r6 ks_r5 ks_r4 ks_r3 ks_r2 ks_r1 ks_r0 06h 00h r/w reserved reserved reserved reserved iod19 iod18 iod17 iod16 07h 00h r/w iod15 iod14 iod13 io d12 iod11 iod10 iod9 iod8 08h 00h r/w iod7 iod6 iod5 io d4 iod3 iod2 iod1 iod0 09h 00h r/w reserved reserved reserved reserved inten19 inten18 inten17 inten16 0ah 00h r/w inten15 inten14 inten13 inten12 inten11 inten10 inten9 inten8 0bh 00h r/w inten7 inten6 inten5 inten4 inten3 inten2 inten1 inten0 0ch 00h r/w reserved reserved reserved reserved gpo19 gpo18 gpo17 gpo16 0dh 00h r/w gpo15 gpo14 gpo13 gpo12 gpo11 gpo10 gpo9 gpo8 0eh 00h r/w gpo7 gpo6 gpo5 gpo4 gpo3 gpo2 gpo1 gpo0 0fh 00h r/w reserved reserved reserved reserved xpd19 xpd18 xpd17 xpd16 10h 00h r/w xpd15 xpd14 xpd13 xpd12 xpd11 xpd10 xpd9 xpd8 11h 00h r/w xpu7 xpu6 xpu5 xpu4 xpu3 xpu2 xpu1 xpu0 12h 00h r/w reserved reserved reserved reserved reserved reserved reserved intflt 13h 00h - reserved reserved reserved reserved reserved reserved reserved reserved 14h 00h r keycode 15h 00h r reserved reserved reserved reserved reserved reserved fifo_ovf fifo_ind 16h 00h r reserved reserved reserved reserved gpi19 gpi18 gpi17 gpi16 17h 00h r gpi15 gpi14 gpi13 gpi12 gpi11 gpi10 gpi9 gpi8 18h ffh r gpi7 gpi6 gpi5 gpi4 gpi3 gpi2 gpi1 gpi0 *1 do not write more than 0x7f in ks_rate do not write ?1? in the reserved resisters. the writ e commands to 13h-18h addresses? registers are ignored.
technical note 16/25 bu1852guw, bu1852gxw www.rohm.com 2012.08 - rev.b ? 2012 rohm co., ltd. all rights reserved. table2 register function symbol address description reset 00h software reset. all registers are initialized by writing "1". this register value is returned to "0" automatically. exceptionally, gpin register is not initialized. clksel 01h ?1? : external clock from xi is used. ?0? : internal cr oscillator is used. ks_rate 02h key scan rate control ks_cx 03h-04h when set to ?1?, port is used as colx for key scan. when set to ?0?, it is used as gpio port. ks_ry 05h when set to ?1?, port is used as rowy for key scan. when set to ?0?, it is used as gpio port. iodn 06h-08h gpion?s io direction. when set to ?1?, gpion direction is output. when set to ?0?, gpion direction is input. intenn 09h-0bh interrupt of gpion port is enabled by "1". it is masked by "0". gpon 0ch-0eh output value of gpion port. xpdn 0fh-10h pull-down of gpion port is on by "0" and off by "1". gpion should be input. xpun 11h pull-up of gpion port is on by "0" and off by "1". gpion should be input. intflt 12h ?1? : interrupt filter on (1us pulse rejection) ?0? : interrupt filter off (bypass) keycode 14h keycode that host can read currently fifo_ind 15h when there are keycode data in fifo, fifo_ind is set to ?1?. ?0? means fifo empty. fifo_ovf 15h when fifo overflow happens, fifo_ov f is set to ?1?. initially ?0? is stored. gpin 16h-18h input value of gpion port. write command is ignored. when interrupt happens, these registers must be read. each bit is valid only when wrseln=0(input). the bits at wrseln=1(output) are fixed. "n" is the number of gpio[19:0] ports. ?x? is the num ber of col[11:0]. ?y? is the number of row[7:0].
technical note 17/25 bu1852guw, bu1852gxw www.rohm.com 2012.08 - rev.b ? 2012 rohm co., ltd. all rights reserved. 5. gpio function gpio configuration when some ports of col[11:0] and row[7: 0] are needed to be used as gpio, tw must be ?0?. then, set the proper value in the appropriate registers through i 2 c. row[7:0] and col[11:0] corre spond to gpio[7:0] and gpio[19:8], respectively. by default, gpio[19:0] ports are set to input(iodn=0) and pull-up/down on(xpun/xpdn=0). (n is the number of gpio[19:0] ports.) refer to the following for the configuration of gpio. table3 gpio configuration state of gpio register gpon iodn xpdn/xpun input, pull-up/down on * 0 0 input, pull-up/down off * 0 1 output, h drive 1 1 * output, l drive 0 1 * output, hi-z 1 0 0 1 1 it is required to pull-up to more than vdd potential. how to deal with gpio ports which are not using when set to output, gpio port must be open. when set to input, don?t make gpio port open. it must be forced by "0" or pull-up/down on. interrupt configuration the initial xint output is hi-z, so it should be pull-up. when interrupt is gen erated, xint port out puts l. by default, interrupt is masked with inten register "0". the bit to be used is made "1", and then the mask is released. in this case, iod register should be "0"(input). write to gpio port after master sets the internal register addr ess for write, the data is sent from msb. after acknowledge is returned, the value of each gpio port will be changed. write configuration pulse, which is tr igger of changing registers, is generat ed at the timing of acknowledge. s x x x x x x x 0 ack ack reg address msb lsb ack data1 (gpo[7:0]) msb lsb p 123456789 scl sda start condition write acknowledge from slave gpio[7:0] acknowledge from slave stop condition data1 valid t dv write configuration pulse s x x x x x x x 0 ack ack reg address msb lsb ack data1 (gpo[7:0]) msb lsb ack wrsel = write mode msb lsb p data1 valid 123456789 scl sda start condition write acknowledge from slave gpio[7:0] acknowledge from slave acknowledge from slave t dv stop condition write configuration pulse fig.16 write to gpio port
technical note 18/25 bu1852guw, bu1852gxw www.rohm.com 2012.08 - rev.b ? 2012 rohm co., ltd. all rights reserved. read from gpio port after writing of the slave address and r/w bits by master, reading gpio port procedure begins. all ports? status that is set to the input by iod regist ers are taken into the gpi register when ack is sent. fig.17 read from gpio port interrupt valid/reset when the gpio interrupt is used, some of inten registers are required to be written to "1". when current gpio port status becomes different from the va lue of the gpin registers, xint port is changed from "1" to "0". after reading gpi regist er, it will return to "1". when master detects interrupt, master must read all gpi r egisters that is set to input(iodn=0), even if xint is changed while reading. it is because bu1852 does not latch the xint status. fig.18 show s one of the example of using only row[7:0] as gpi. in this case, master r eads only 18h register immediate after detecting xint. xint cannot distinguish whether just one port is different or multi ports are different from the prev ious value. master is necessary to store the previous gpi register value and co mpare it with the current value after xint is asserted. stop condition s x x x x x x x 1 ack na scl sda start condition read acknowledge from slave gpion data2 (gpi[7:0]) msb lsb data1 data2 p no acknowledge from master t iv t ir xint data1 data2 gpin reg 123456789 data3 data2 t iv t ir fig.18 interrupt valid/reset (example : row[7:0] as gpi with interrupt) stop condition s x x x x x x x 1 a c k scl sd a start condition read a cknowledge from slave gpio[7:0] d1 p no acknowledge from maste r 123456789 na d1 [7] d1 [6] d1 [5] d2 d1 [4] d 1 [3] d 1 [2] d1 [1] d1 [0] gpi[7:0] reg d1
technical note 19/25 bu1852guw, bu1852gxw www.rohm.com 2012.08 - rev.b ? 2012 rohm co., ltd. all rights reserved. 6. key code assignment table 4 shows the key code assignment. these key codes are sent through 3wire or i 2 c corresponding to the pushed or released keys. table4 key codes m : make key (the code when the key is pressed) b : break key (the code when the key is released) row 0 row 1 row 2 row 3 row 4 row 5 row 6 row 7 0x01 0x11 0x21 0x31 0x41 0x51 0x61 0x71 m 0x81 0x91 0xa1 0xb1 0xc1 0xd1 0xe1 0xf1 b m b m b m b m b m b m b m col 0 col 1 col 2 col 3 col 4 col 5 col 6 col 7 b 0x02 0x12 0x22 0x32 0x42 0x52 0x62 0x72 0x82 0x92 0xa2 0xb2 0xc2 0xd2 0xe2 0xf2 0x03 0x13 0x23 0x33 0x43 0x53 0x63 0x73 0x83 0x93 0xa3 0xb3 0xc3 0xd3 0xe3 0xf3 0x04 0x14 0x24 0x34 0x44 0x54 0x64 0x74 0x84 0x94 0xa4 0xb4 0xc4 0xd4 0xe4 0xf4 0x05 0x15 0x25 0x35 0x45 0x55 0x65 0x75 0x85 0x95 0xa5 0xb5 0xc5 0xd5 0xe5 0xf5 0x06 0x16 0x26 0x36 0x46 0x56 0x66 0x76 0x86 0x96 0xa6 0xb6 0xc6 0xd6 0xe6 0xf6 0x07 0x17 0x27 0x37 0x47 0x57 0x67 0x77 0x87 0x97 0xa7 0xb7 0xc7 0xd7 0xe7 0xf7 0x08 0x18 0x28 0x38 0x48 0x58 0x68 0x78 0x88 0x98 0xa8 0xb8 0xc8 0xd8 0xe8 0xf8 m col 8 b 0x09 0x19 0x29 0x39 0x49 0x59 0x69 0x79 0x89 0x99 0xa9 0xb9 0xc9 0xd9 0xe9 0xf9 m col 9 b 0x0 a 0x1 a 0x2 a 0x3 a 0x4 a 0x5 a 0x6 a 0x7 a 0x8 a 0x9 a 0xa a 0xba 0xca 0xd a 0xea 0xf a m col 10 b 0x0b 0x1b 0x2b 0x3b 0x4b 0x5b 0x6b 0x7b 0x8b 0x9b 0xab 0xbb 0xcb 0xdb 0xeb 0xfb m col 11 b 0x0c 0x1c 0x2c 0x3c 0x4c 0x5c 0x6c 0x7c 0x8c 0x9c 0xac 0xbc 0xcc 0xdc 0xec 0xfc
technical note 20/25 bu1852guw, bu1852gxw www.rohm.com 2012.08 - rev.b ? 2012 rohm co., ltd. all rights reserved. 7. ghost key rejection ghost key is an inevitable phenomenon as long as key-switch matrices are used. when thr ee switches located at the corners of a certain matrix rectangle are pressed simultaneously , the switch that is located at the last corner of the rectangle (the ghost key) also appears to be pressed, even t hough the last key is not pressed. this occurs because the ghost key switch is electrically shorted by the combinatio n of the other three switches (fig.19). because the key appears to be pressed electrically, it is impossible to distin guish which key is the ghost key and which key is pressed. the bu1852 solves the ghost key problem to use the simp le method. if bu1852 detects any three-key combination that generates a fourth ghost key, and bu1852 does not r eport anything, indicating the ghost keys are ignored. this means that many combinations of three keys are also ignored when pressed at the same time. applications requiring three-key combinations (such as ) must ens ure that the three keys are not wired in positions that define the vertices of a rectangle (fig. 20). there is no limit on the number of ke ys that can be pressed simultaneously as long as the keys do not generate ghost key events. ghost-key event pressed key event key-switch matrix fig.19 ghost key phenomenon key-switch matrix key-switch matrix examples of valid three-key combinations fig.20 valid three key combinations
technical note 21/25 bu1852guw, bu1852gxw www.rohm.com 2012.08 - rev.b ? 2012 rohm co., ltd. all rights reserved. 8. recommended flow fig.21 shows the recommended flow when tw=0(i 2 c protocol is selected). power on reset release clock select assign each port to key scan and gpio detemine gpio direction gpi interrupt setting control gpo port or monitor xint related registers determine key scan rate 01h : clksel 02h : ks_rate 03h-04h : ks_c[11:0] 05h : ks_r[7:0] 06h-08h : iod[19:0] 09h-0bh : inten[19:0] 0ch-0eh : gpo[19:0] 14h-18h : read registers sequence 12h : intflt fig.21 recommended flow and related registers forbidden operation: --- dynamic change of tw (i 2 c/3wire protocol should be fixed) --- dynamic assignment change of keyscan and gpio (should be determined initially) --- dynamic change of keyscan rate (should be determi ned initially) --- dynamic change of clksel (sho uld be determined initially)
technical note 22/25 bu1852guw, bu1852gxw www.rohm.com 2012.08 - rev.b ? 2012 rohm co., ltd. all rights reserved. application circuit example scl bu1852guw mpu vss 0.1uf 1.8v vdd row0 sda int xint xrst scl sda testm[1:0] row7 row1 row2 row3 row4 row5 row6 col0 col1 col2 col3 col4 col5 col6 col7 xi vddio porenb tw adr vdd col8 col9 col10 col11 vss 1.8v to other i 2 c devices gpo gpi 3.0v 0.1uf from/to 3.0v device fig.22 application circuit example
technical note 23/25 bu1852guw, bu1852gxw www.rohm.com 2012.08 - rev.b ? 2012 rohm co., ltd. all rights reserved. appendix 1. 3wire interface (tw=?1?) sda scl xint bit7 bit6 bit5 bit0 invalid start bit sent by bu1852 sent by host device fig.23 3wire protocol figure 23 shows the original 3wire protocol of bu1852. when th is 3wire protocol is used, tw must be ?1?. note that this 3wire interface is completely different from i 2 c and other standard bus interface. procedure 1. when bu1852 detects key events, xint interr upt is generated to host with driving low. 2. after the host detects xint interrup t, the host is supposed to send start bit. 3. after bu1852 detects start bit, the 8bit data (key code) transmission on sda will start synchronized with the rising edge of scl clock signal, which is sent from the host. 4. 8 bit data are followed by ?0? (9 th bit is always ?0?), and then bu1852 drives high on xint line. see also section ?3wire interface ac characteristics?.
technical note 24/25 bu1852guw, bu1852gxw www.rohm.com 2012.08 - rev.b ? 2012 rohm co., ltd. all rights reserved. 2. 3wire interface ac characteristics fig.24 3wire interface ac timing vdd=1.8v, vddio=1.8v,topr=25 ,tw=vdd parameter symbol limits unit conditions min. typ. max. scl clock frequency f twsclk - - 21.5 khz start condition setup time t twsu;sta 0.030 - 500 ms start condition hold time t twhd;sta 20 - - s scl low time t twlow;clk 23 - - s scl high time t twhigh;clk 23 - - s data hold time t twhd;dat 0.1 - 1.0 s xint end hold t twhd;inte 1.35 - 10.2 s xint low time t twlow;int 500 800 1350 ms scl sda t tws u ;st a t twh d ;st a t twl ow ; clk t twh igh ; clk 1 / f tws clk start bit 7 bit 6 "0 " state xint bit 0 t twhd ;inte t twh d ;dat t twlow ;int
technical note 25/25 bu1852guw, bu1852gxw www.rohm.com 2012.08 - rev.b ? 2012 rohm co., ltd. all rights reserved. ordering part number b u 1 8 5 2 g u w - e 2 part no. part no. package guw: vbga035w040 gxw: ubga035w030 packaging and forming specification e2: embossed tape and reel (unit : mm) vbga035w040 m ab s 0.05 35- 0.295 0.05 0.08 s s a b 1pin mark 4.0 0.1 4.0 0.1 0.9max. 0.10 f e d c b a 123456 p=0.5 5 0.75 0.1 0.5 0.75 0.1 p=0.5 5 ? order quantity needs to be multiple of the minimum quantity. embossed carrier tape (with dry pack) tape quantity direction of feed the direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand 2500pcs e2 () direction of feed reel 1pin ? order quantity needs to be multiple of the minimum quantity. embossed carrier tape (with dry pack) tape quantity direction of feed the direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand 1000pcs e2 () direction of feed reel 1pin ubga035w030 (unit : mm) e c f d a b 356 24 1 0.08 s 3.0 0.1 3.0 0.1 0.9max 0.5 0.1 p=0.4 5 p=0.4 5 0.4 0.4 0.1 s a b 1pin mark 35- 0.2 0.05 0.5 0.1 b 0.05 a
r1120a www.rohm.com ? 2012 rohm co., ltd. all rights reserved. notice rohm customer support system http://www.rohm.com/contact/ thank you for your accessing to rohm product informations. more detail product informations and catalogs are available, please contact us. notes no copying or reproduction of this document, in part or in whole, is permitted without the consent of rohm co.,ltd. the content specified herein is subject to change for improvement without notice. the content specified herein is for the purpose of introducing rohm's products (hereinafter "products"). if you wish to use any such product, please be sure to refer to the specifications, which can be obtained from rohm upon request. examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the products. the peripheral conditions must be taken into account when design ing circuits for mass production. great care was taken in ensuring the accuracy of the information specified in this document. however, should you incur any damage arising from any inaccuracy or misprint of such information, rohm shall bear no responsibility for such damage. the technical information specified herein is intended only to show the typical functions of and examples of application circuits for the produc ts. rohm does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by rohm and other parties. rohm shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. the products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, commu- nication devices, electronic appliances and amusement devices). the products specified in this document are not designed to be radiation tolerant. while rohm always makes efforts to enhance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment using the products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any product, such as derating, redundancy, fire control and fail-safe designs. rohm shall bear no responsibility whatsoever for your use of any product outside of the prescribed scope or not in accordance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel- controller or other safety device). rohm shall bear no responsibility in any way for use of any of the products for the above special purposes. if a product is intended to be used for any such special purpose, please contact a rohm sales representative before purchasing. if you intend to export or ship overseas any product or technology specified herein that may be controlled under the foreign exchange and the foreign trade law, you will be required to obtain a license or permit under the law.

▲Up To Search▲

Price & Availability of BU1852GUW12

	To Download BU1852GUW12 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .